View EVAL-AD5533EB_3257345.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5533b * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 32-channel precision infinite sample-and-hold features infinite sample-and-hold capability to 0.018% accuracy infinite sample-and-hold total unadjusted error 2.5 m v high integration: 32-channel dac in 12 mm 12 mm cspbga per channel acquisition time of 16 s max adjustable voltage output range output impedance 0.5 output voltage span 10 v readback capability dsp/microcontroller compatible serial interface parallel interface temperature range C 40 c to +85 c applications optical networks automatic test equipment level setting instrumentation industrial control systems data acquisition low cost i/o functional block diagram sync / cs wr cal a4a0 sclk o ffset sel ad5533b dv cc v in d in d out address input register av cc ref in ref out offs in interface control logic offs out v out 31 v out 0 track / reset busy dac gnd agnd dgnd ser / par v dd v ss dac dac dac adc general description the ad5533b combines a 32-channel voltage translation function with an infinite output hold capability. an analog input voltage on the common input pin, v in , is sampled and its digital represen- tation transferred to a chosen dac register. v out for this dac is then updated to reflect the new contents of the dac register. channel selection is accomplished via the parallel address inputs a0?4 or via the serial input port. the output voltage range is determined by the offset voltage at the offs_in pin and the gain of the output amplifier. it is restricted to a range from v ss + 2 v to v dd ?2 v because of the headroom of the output amplifier. the device is operated with av cc = +5 v 5%, dv cc = +2.7 v to +5.25 v, v ss = ?.75 v to ?6.5 v, and v dd = +8 v to +16.5 v and requires a stable 3 v reference on ref_in as well as an offset voltage on offs_in. product highlights 1. precision infinite droopless sample-and-hold capability. 2. the ad5533b is available in a 74-lead cspbga with a body size of 12 mm 12 mm. 3. in infinite sample-and-hold mode, a total unadjusted e rror of 2.5 mv is achieved by laser-trimming on-chip resistors. * protected by u.s. patent no. 5,969,657; other patents pending.
rev. a e2e ad5533b especifications (v dd = +8 v to +16.5 v, v ss = e4.75 v to e16.5 v; av cc = +4.75 v to +5.25 v; dv cc = 2.7 v to 5.25 v; agnd = dgnd = dac_gnd = 0 v; ref_in = 3 v; offs_in = 0 v; output range from v ss + 2 v to v dd e 2 v. all outputs unloaded. all specifications t min to t max , unless otherwise noted.) parameter 1 b version 2 unit conditions/comments analog channel v in to v out nonlinearity 0.006 % typ input range 100 mv to 2.96 v 0.018 % max after gain and offset adjustment total unadjusted error (tue) 2.5 mv typ see tpc 6. 12 mv max gain 3.51/3.52/3.53 min/typ/max offset error 1 mv typ see tpc 2. 10 mv max analog input (v in ) input voltage range 0 to 3 v nominal input range input lower dead band 70 mv max 50 mv typ. referred to v in . see figure 5. input upper dead band 40 mv max 12 mv typ. referred to v in . see figure 5. input current 1 a max 100 na typ. v in acquired on one channel. input capacitance 3 20 pf typ analog input (offs_in) input voltage range 0/4 v min/max output range restricted from v ss + 2 v to v dd e 2 v input current 1 a max 100 na typ voltage reference ref_in nominal input voltage 3.0 v input voltage range 3 2.85/3.15 v min/max input current 1 a max <1 na typ ref_out output voltage 3 v typ output impedance 3 280 k typ reference temperature coefficient 3 60 ppm/ c typ analog outputs (v out 0e31) output temperature coefficient 3, 4 10 ppm/ c typ dc output impedance 0.5 typ output range v ss + 2/v dd e 2 v min/max 100 a output load resistive load 3, 5 5 k min capacitive load 3, 5 100 pf max short-circuit current 3 7 ma typ dc power supply rejection ratio 3 e70 db typ v dd = +15 v 5% e70 db typ v ss = e15 v 5% dc crosstalk 3 250 v max outputs loaded analog output (offs_out) output temperature coefficient 3, 4 10 ppm/ c typ dc output impedance 3 1.3 k typ output range 50 to ref_in e 12 mv typ output current 10 a max source current capacitive load 100 pf max digital inputs 3 input current 10 a max 5 a typ input low voltage 0.8 v max dv cc = 5 v 5% 0.4 v max dv cc = 3 v 10% input high voltage 2.4 v min dv cc = 5 v 5% 2.0 v min dv cc = 3 v 10% input hysteresis ( sclk cs c
rev. a e3e ad5533b parameter 1 b version 2 unit conditions/comments digital outputs ( busy , d out ) 3 output low voltage 0.4 v max dv cc = 5 v. sinking 200 = = = = = = = = = = = = = = ?
rev. a e4e ad5533b timing characteristics parallel interface limit at t min , t max parameter 1, 2 (b version) unit conditions/comments t 1 0 ns min cs to wr setup time t 2 0 ns min cs to wr hold time t 3 50 ns min cs pulsewidth low t 4 50 ns min wr pulsewidth low t 5 20 ns min a4ea0, cal, offs_sel to wr setup time t 6 7 ns min a4ea0, cal, offs_sel to wr hold time notes 1 see parallel interface timing diagram. 2 guaranteed by design and characterization, not production tested. specitcations subject to change without notice. serial interface limit at t min , t max parameter 1, 2 (b version) unit conditions/comments f clkin 20 mhz max sclk frequency t 1 20 ns min sclk high pulsewidth t 2 20 ns min sclk low pulsewidth t 3 15 ns min sync falling edge to sclk falling edge setup time t 4 50 ns min sync low time t 5 10 ns min d in setup time t 6 5 ns min d in hold time t 7 5 ns min sync falling edge to sclk rising edge setup time for readback t 8 3 20 ns max sclk rising edge to d out valid t 9 3 60 ns max sclk falling edge to d out high impedance t 10 400 ns mi n1 0th sclk falling edge to sync falling edge for readback t 11 4 7 ns mi n sclk falling edge to sync falling edge setup time for readback notes 1 see serial interface timing diagrams. 2 guaranteed by design and characterization, not production tested. 3 these numbers are measured with the load circuit of figure 2. 4 sync should be taken low while sclk is low for readback. specitcations subject to change without notice. parallel interface timing diagram cs wr aa ca ffs se f pwsa a a c f t utput pn f c ut ts
rev. a e5e ad5533b serial interface timing diagrams 12345678 910 t 1 t 2 t 3 t 4 t 5 t 6 msb lsb sclk sync d in figure 3. 10-bit write (isha mode and both readback modes) 2 134567 8 9 10 11 12 13 14 msb lsb sclk s ync d out 10 t 11 t 10 t 1 t 2 t 4 t 8 t 9 t 7 figure 4. 14-bit read (both readback modes)
rev. a e6e ad5533b ordering guide output output impedance voltage span package package description function (typ) (v) description option ad5533bbc-1 32-channel precision isha only 0.5 10 74-lead cspbga bc-74 ad5533abc-1 * 32-channel isha only 0.5 10 74-lead cspbga bc-74 ad5532abc-1 * 32 dacs, 32-channel isha 0.5 10 74-lead cspbga bc-74 ad5532abc-2 * 32 dacs, 32-channel isha 0.5 20 74-lead cspbga bc-74 ad5532abc-3 * 32 dacs, 32-channel isha 500 10 74-lead cspbga bc-74 ad5532abc-5 * 32 dacs, 32-channel isha 1 k 10 74-lead cspbga bc-74 ad5532bbc-1 * 32 dacs, 32-channel precision isha 0.5 10 74-lead cspbga bc-74 EVAL-AD5533EB ad5532/ad5533 evaluation board * separate data sheet absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +17 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to e17 v av cc to agnd, dac_gnd . . . . . . . . . . . . . e0.3 v to +7 v dv cc to dgnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v digital inputs to dgnd . . . . . . . . . . e0.3 v to dv cc + 0.3 v digital outputs to dgnd . . . . . . . . . e0.3 v to dv cc + 0.3 v ref_in to agnd, dac_gnd . . . . e0.3 v to av cc + 0.3 v v in to agnd, dac_gnd . . . . . . . . e0.3 v to av cc + 0.3 v v out 0e31 to agnd . . . . . . . . . . v ss e 0.3 v to v dd + 0.3 v offs_in to agnd . . . . . . . . . . v ss e 0.3 v to v dd + 0.3 v offs_out to agnd . . . . agnd e 0.3 v to av cc + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v operating temperature range industrial . . . . . . . . . . . . . . . . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature (t j m ax) . . . . . . . . . . . . . . . . . . 150 c 74-lead cspbga package, ja thermal impedance . . 41 c/w reflow soldering peak temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c time at peak temperature . . . . . . . . . . . . 10 sec to 40 sec max power dissipation . . . . . . . . . . . . (150 c e t a )/ ja mw 3 max continuous load current at t j = 70 c, per channel group . . . . . . . . . . . . . . . . . . . . . . . 15.5 ma 4 notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operationa l sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. 3 this limit includes load power. 4 this maximum allowed continuous load current is spread over eight channels, with channels grouped as follows: group 1: channels 3, 4, 5, 6, 7, 8, 9, 10 group 2: channels 14, 16, 18, 20, 21, 24, 25, 26 group 3: channels 15, 17, 19, 22, 23, 27, 28, 29 group 4: channels 0, 1, 2, 11, 12, 13, 30, 31 for higher junction temperatures, derate as follows: max continuous load current t j ( c) per group (ma) 70 15.5 90 9.025 100 6.925 110 5.175 125 3.425 135 2.55 150 1.5 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5533b features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a ad5533b e7e pin configuration 1234567891011 a b c d e f g h j k l 12345 67891011 a b c d e f g h j k l 74-lead cspbga ball contguration cspbga ball cspbga ball cspbga ball number name number name number name a1 nc * c10 avcc1 j10 vo9 a2 a4 c11 ref_out j11 vo11 a3 a2 d1 vo20 k1 vo17 a4 a0 d2 dac_gnd2 k2 vo15 a5 cs sync acc k a cc sut k ss a sclk e k ss a setsel e k ss a busy e an k a track reset e sn k a nc k b k b nc an k b a l nc b a l b wr l b n l b n l b cal h l b ser par h n l b ut h l b ren h l c l c acn l nc c nc ss nc n c
rev. a e8e ad5533b pin function descriptions pin function agnd (1e2) analog gnd pins av cc (1e2) analog supply pins. voltage range from 4.75 v to 5.25 v. v dd (1e4) v dd supply pins. voltage range from 8 v to 16.5 v. v ss (1e4) v ss supply pins. voltage range from e4.75 v to e16.5 v. dgnd digital gnd pins dv cc digital supply pins. voltage range from 2.7 v to 5.25 v. dac_gnd (1e2) reference gnd supply for all the dacs ref_in reference voltage for channels 0e31 ref_out reference output voltage v out (0e31) analog output voltages from the 32 channels v in analog input voltage a4ea1 1 , a0 2 parallel interface. 5-address pins for 32 channels. a4 = msb of channel address. a0 = lsb. cal 1 parallel interface. control input that allows all 32 channels to acquire v in simultaneously. cs / sync this pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for the serial interface. wr 1 parallel interface. write pin. active low. this is used in conjunction with the cs pin to address the device using the parallel interface. offset_sel 1 parallel interface. offset select pin. active high. this is used to select the offset channel. sclk 2 serial clock input for serial interface. this operates at clock speeds up to 20 mhz. d in 2 data input for serial interface. data must be valid on the falling edge of sclk. d out output from the dac registers for readback. data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. ser/ par 1 this pin allows the user to select whether the serial or parallel interface will be used. if the pin is tied low, the parallel interface will be used. if it is tied high, the serial interface will be used. offs_in offset input. the user can supply a voltage here to offset the output span. offs_out can also be tied to this pin if the user wants to drive this pin with the offset channel. offs_out o ffset output. this is the acquired/programmed offset voltage that can be tied to the offs_in pin to offset the span. busy this output tells the user when the input voltage is being acquired. it goes low during acquisition and returns high when the acquisition operation is complete. track / reset 2 if this input is held high, v in is acquired once the channel is addressed. while it is held low, the input to the gain/offset stage is switched directly to v in . the addressed channel begins to acquire v in on the rising edge of track . see track input section for further information. this input can also be used as a means of resetting the complete device to its power-on-reset conditions. this is achieved by applying a low going pulse of between 90 ns and 200 ns to this pin. see section on reset function for further details. notes 1 internal pull-down devices on these logic inputs. therefore, they can be left floating and will default to a logic low conditio n. 2 internal pull-up devices on these logic inputs. therefore, they can be left floating and will default to a logic high condition .
rev. a ad5533b e9e terminology v in to v out nonlinearity this is a measure of the maximum deviation from a straight line passing through the endpoints of the v in versus v out transfer function. it is expressed as a percentage of the full-scale span. total unadjusted error (tue) this is a comprehensive specification that includes relative accu- racy, gain, and offset errors. it is measured by sampling a range of voltages on v in and comparing the measured voltages on v out to the ideal value. it is expressed in mv. offset error this is a measure of the output error when v in = 70 mv. ideally, with v in = 70 mv: vg ain gain v mv out offs in =? ? ()(()) _ 70 1 offset error is a measure of the difference between v out (actual) and v out (ideal). it is expressed in mv and can be positive or negative. see figure 5. gain error this is a measure of the span error of the analog channel. it is the deviation in slope of the transfer function. see figure 5. it is calculated as: gain error actual full scale output ideal full scale output offset error =? ? - - where ideal full scale output gain gain v offs in - =? ? (.)(() ) _ 296 1 ideal gain = 3.52 output temperature coefficient this is a measure of the change in analog output with changes in temperature. it is expressed in ppm/
rev. a ?0 ad5533btypical performance characteristics v in ?v 0.0024 0.0000 ?.0024 0.1 2.96 v out error ?v 0.0020 0.0004 ?.0004 ?.0012 0.0012 0.0008 ?.0008 0.0016 ?.0020 ?.0016 t a = 25 c v refin = 3v v offs_in = 0v tpc 1. v in to v out accuracy after offset and gain adjustment temperature ? c 4 3 0 ?0 120 0 offset error ?mv 40 80 2 1 offset error gain 3.530 3.525 3.500 gain 3.520 3.515 tpc 2. offset error and gain vs. temperature sink/source current ?ma 3.530 3.525 3.515 66 4 v out ?v 202 ? 3.520 t a = 25 c v refin = 3v v in = 1v tpc 3. v out source and sink capability 100 90 10 0% busy t a = 25 c v refin = 3v v in = 0v to 1.5v v out 5v 1v 2 s tpc 4. acquisition time and output settling time v out ?v 70k 60k 0 5.2670 5.2682 5.2676 frequency 40k 30k 20k 10k 50k 63791 200 1545 t a = 25 c v refin = 3v v in = 1.5v v offs_in = 0v tpc 5. isha mode repeatability (64 k acquisitions) to ta l unadjusted error ?mv 40 20 0 ? 8 ? frequency ? ? 0 1 2 3 4 5 6 7 tpc 6. tue distribution at 25 c (isha mode)
rev. a ad5533b ?1 track v in dac acquisition circuit v out 1 busy output stage controller threshold voltage pin driver device under test only one channel shown for simplicity ad5533b controller output stage acquisition circuit figure 7. typical ate circuit using track input functional description the ad5533b can be thought of as consisting of an adc and 32 dacs in a single package. the input voltage v in is sampled and converted into a digital word. the digital result is loaded into one of the dac registers and is converted (with gain and offset) into an analog output voltage (v out 0? out 31). since the chan- nel output voltage is effectively the output of a dac there is no droop associated with it. as long as power to the device is main- tained, the output voltage will remain constant until this channel is addressed again. to update a single channel? output voltage, the required new voltage level is set up on the common input pin, v in . the desired channel is then addressed via the parallel port or the serial port. when the channel address has been loaded, provided track is high, the circuit begins to acquire the correct code to load to the dac so that the dac output matches the voltage on v in . the busy pin goes low and remains so until the acquisition is com- plete. the noninverting input to the output buffer is tied to v in during the acquisition period to avoid spurious outputs while the dac acquires the correct code. the acquisition is completed in 16 s max. the busy pin goes high and the updated dac output assumes control of the output voltage. the output voltage of the dac is connected to the noninverting input of the output buffer. since the internal dacs are offset by 70 mv (max) from gnd, the minimum v in in isha mode is 70 mv. the maximum v in is 2.96 v due to the upper dead band of 40 mv (max). on power-on, all the dacs, including the offset channel, are loaded with zeros. each of the 33 dacs is offset internally by 50 mv (typ) from gnd so the outputs v out 0 to v out 31 are 50 mv (typ) on power-on if the offs_in pin is driven directly by the on-board offset channel (offs_out), i.e., if offs_in = offs_out = 50 mv = > v out = (gain v dac ) ?(gain ?1) v offs_in = 50 mv. analog input the equivalent analog input circuit is shown in figure 6. the c apacitor c1 is typically 20 pf and can be attributed to pin capaci- tance and 32 off-channels. when a channel is selected, an extra 7.5 pf (typ) is switched in. this capacitor c2 is charged to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. it is essential that the external source can charge/discharge this additional capacitance within 1 s? s of channel selection so that v in can be acquired accu- rately. for this reason, a low impedance source is recommended. c1 20pf v in c2 7.5pf addressed channel figure 6. analog input circuit large source impedances will significantly affect the performance of the adc. this may necessitate the use of an input buffer amplifier. output buffer stage?ain and offset the function of the output buffer stage is to translate the 50 mv? v typical output of the dac to a wider range. this is done by gaining up the dac output by 3.52 and offsetting the voltage by the voltage on offs_in pin. v 3.52 v 2.52 v out dac offs_in = ? v dac is the output of the dac. v offs_in is the voltage at the offs_in pin. table i shows how the output range on v out relates to the offset voltage supplied by the user. table i. sample output voltage ranges v offs_in (v) v dac (v) v out (v) 0 0.05 to 3 0.176 to 10.56 1 0.05 to 3 ?.34 to +8.04 2.130 0.05 to 3 ?.192 to +5.192 v out is limited only by the headroom of the output amplifiers. v out must be within maximum ratings. offset voltage channel the offset voltage can be externally supplied by the user at offs_in or it can be supplied by an additional offset voltage channel on the device itself. the required offset voltage is set up on v in and acquired by the offset dac. this offset channel? dac output is directly connected to offs_out. by connecting offs_out to offs_in, this offset voltage can be used as the offset voltage for the 32 output amplifiers. it is important to choose the offset so that v out is within maximum ratings.
rev. a ?2 ad5533b reset function the reset function on the ad5533b can be used to reset all nodes on this device to their power-on-reset condition. this is implemented by applying a low-going pulse of between 90 ns and 200 ns to the track / reset pin on the device. if the applied pulse is less than 90 ns, it is assumed to be a glitch and no opera- tion takes place. if the applied pulse is wider than 200 ns , this pin adopts its track function on the selected channel, v in is switched to the output buffer, and an acquisition on the channel will not occur until a rising edge of track . track function normally in isha mode of operation, track is held high and the channel begins to acquire when it is addressed. however, if track is low when the channel is addressed, v in is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of track . at this stage the busy pin will go low until the acquisition is complete, at which point the dac assumes control of the voltage to the output buffer and v in is free to change again without affecting this output value. this is useful in an application where the user wants to ramp up v in until v out reaches a particular level (figure 7). v in does n ot need to be acquired continuously while it is ramping up. track can be kept low and only when v out has reached its d esired voltage is track brought high. at this stage, the ac quisition of v in begins. in the example shown, a desired voltage is required on the output of the pin driver. this voltage is represented by one input to a comparator. the microcontroller/microprocessor ramps up the input voltage on v in through a dac. track is kept low while t he voltage on v in ramps up so that v in is not continu ally acquired. when the desired voltage is reached on the output of the pin driver, the comparator output switches. the c/ p then k nows what code is required to be input in order to obtain the desired voltage at the dut. the track input is now brought high and the part begins to acquire v in . busy goes low until v in has been acquired. when busy goes high, the output buffer is switched from v in to the output of the dac. modes of operation the ad5533b can be used in three different modes. these m odes are set by two mode bits, the first two bits in the serial word. the 01 option (dac mode) is not available for the ad5533b. for information on this mode, refer to the ad5532b data sheet. if yo u attempt to set up dac mode, the ad5533b will enter a test mode and a 24-clock write will be necessary to clear this. table ii. modes of operation mode bit 1 mode bit 2 operating mode 00 is ha mode 01 dac mode (not available) 10 acquire and readback 11 readback 1. isha mode in this standard mode, a channel is addressed and that c hannel acquires the voltage on v in . this mode requires a 10-bit write (see figure 3) to address the relevant channel (v out 0? out 31, offset channel, or all channels). msb is written first. 2. acquire and readback mode this mode allows the user to acquire v in and read back the data in a particular dac register. the relevant channel is addressed (10-bit write, msb first) and v in is acquired in 16 s (max). following the acquisition, after the next falling edge of sync , the data in the relevant dac register is clocked out onto the d out line in a 14-bit serial format (see figure 4). during readback, d in is ignored. the full acquisition time must elapse before the dac register data can be clocked out. 3. readback mode again, this is a readback mode but no acquisition is per formed. the relevant channel is addressed (10-bit write, msb first) and on the next falling edge of sync , the data in the relevant dac register is clocked out onto the d out line in a 14-bit serial format (see figure 4). t he user must allow 400 ns (min) between the last sclk falling edge in the 10-bit write and the falling edge of sync in the 14-bit readback. the serial write and read words can be seen in figure 8. this feature allows the user to read back the dac register code of any of the channels. readback is useful if the system has been calibrated and the user wants to know what code in the dac corresponds to a desired voltage on v out . interfaces serial interface the ser/ par pin is tied high to enable the serial interface and to disable the parallel interface. the serial interface is controlled by four pins as follows: sync , d in , sclk standard 3-wire interface pins. the sync pin is shared with the cs function of the parallel interface. d out data out pin for reading back the contents of the dac reg isters. the data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. mode bits there are four different modes of operation as described above. cal bit when this is high, all 32 channels acquire v in simultaneously. the acquisition time is then 45 s (typ) and accuracy may be reduced. this bit is set low for normal operation. offset_sel bit if this bit is set high, the offset channel is selected and bits a 4?0 are ignored. test bit this must be set low for correct operation of the part. a4?0 bit u sed to address any one of the 32 channels (a4 = msb of ad dress, a0 = lsb).
rev. a ad5533b ?3 db13?b0 bit these are used in both readback modes to read a 14-bit word from the addressed dac register. the serial interface is designed to allow easy interfacing to most microcontrollers and dsps, e.g., pic16c, pic17c, qspi, sp i , dsp56000, tms320, and adsp-21xx, without the need for any glue logic. when interfacing to the 8051, the sclk must be inverted. the microprocessor/microcontroller interface section explains how to interface to some popular dsps and microcontrollers. figures 3 and 4 show the timing diagram for a serial read and write to the ad5533b. the serial interface works with both a continuous and a noncontinuous serial clock. the first falling edge of sync resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. any further edges on sync are ignored until the correct number of bits are shifted in or out. once the correct number of bits have been shifted in or out, the sclk is ignored. in order for another serial transfer to take place, the counter must be reset by the falling edge of sync . in readback, the first rising sclk edge after the falling edge of sync causes d out to leave its high impedance state and data is clocked out onto the d out line and also on subsequent sclk rising edges. the d out pin goes back into a high impedance state on the falling edge of the 14th sclk. data on the d in line is latched in on the first sclk falling edge after the falling edge of the sync signal and on subsequent sclk falling edges. the serial interface will not shift data in or out until it receives the falling edge of the sync signal. * spi and qspi are trademarks of motorola, inc. offset sel a4?0 cal 0 0 msb lsb mode bit 1 mode bit 2 mode bits 0 test bit a. 10-bit input serial write word (isha mode) offset sel a4?0 cal 0 1 msb lsb mode bits db13?b0 0 test bit 10-bit serial word written to part 14-bit data read from part after next falling edge of sync ( db13 = msb of dac word) msb lsb b. input serial interface (acquire and readback mode) offset sel a4?0 0 1 1 msb lsb mode bits db13?b0 0 test bit 10-bit serial word written to part 14-bit data read from part after next falling edge of sync ( db13 = msb of dac word) msb lsb c. input serial interface (readback mode) figure 8. serial interface formats parallel interface the ser/ par bit is tied low to enable the parallel inter face and disable the serial interface. the parallel interface is controlled by nine pins as follows: cs active low package select pin. this pin is shared with the sync function for the serial interface. wr active low write pin. the values on the address pins are latched on a rising edge of wr . a4?0 five address pins (a4 = msb of address, a0 = lsb). these are used to address the relevant channel (out of a possible 32). offset_sel offset select pin. this has the same function as the offset_sel bit in the serial interface. when it is high, the offset channel is addressed and the address on a4?0 is ignored. cal s ame functionality as the cal bit in the serial interface. when this pin is high, all 32 channels acquire v in simultaneously. microprocessor interfacing ad5533b to adsp-21xx interface the adsp-21xx family of dsps is easily interfaced to the ad5533b without the need for extra logic. a data transfer is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsp? serial clock and clocked into the ad5533b on the falling edge of its sclk. in
rev. a ?4 ad5533b readback, 16 bits of data are clocked out of the ad5533b on each rising edge of sclk and clocked into the dsp on the rising edge of sclk. d in is ignored. the valid 14 bits of data will be centered in the 16-bit rx register when using this configuration. the sport control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right-justify data isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0, external framing signal itfs = 1, internal framing signal slen = 1001, 10-bit data-words (isha mode write) slen = 1111, 16-bit data-words (readback mode) figure 9 shows the connection diagram. sclk ad5533b * d out sync d in dr tfs rfs dt sclk adsp-2101/ adsp-2103 * * additional pins omitted for clarity figure 9. ad5533b to adsp-2101/adsp-2103 interface ad5533b to mc68hc11 the serial peripheral interface (spi) on the mc68hc11 is con?- ured for master mode (mstr = 1), clock polarity bit (cpol) = 0 and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)?see 68hc11 user manual . sck of the 68hc11 drives the sclk of the ad5533b, the mosi output drives the serial data line (d in ) of the ad5533b, and the miso input is driven from d out . the sync signal is derived from a port line (pc7). when data is being transmitted to the ad5533b, the sync line is taken low (pc7). data appear- ing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to transmit 10 data bits in isha mode it is important to left-justify the data in the spdr register. pc7 must be pulled low to start a transfer. it is taken high and pulled low again before any further read/write cycles can take place. a connection diagram is shown in figure 10. sclk ad5533b * d out sync d in miso pc7 sck mc68hc11 * * additional pins omitted for clarity mosi figure 10. ad5533b to mc68hc11 interface ad5533b to pic16c6x/7x the pic16c6x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit = 0. this is done by writing to the synchronous serial port control register (sspcon). see pic16/17 microcontroller user manual . in this example i/o port ra1 is being used to pulse sync and enable the serial port of the ad5533b. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecu- tive read/write operations are needed for a 10-bit write and a 14-bit readback. figure 11 shows the connection diagram. sclk pic16c6x/7x * d out sync d in sck/rc3 ad5533b * * additional pins omitted for clarity sdo/rc5 sdi/ rc4 ra1 figure 11. ad5533b to pic16c6x/7x interface ad5533b to 8051 the ad5533b requires a clock synchronized to the serial data. the 8051 serial interface must therefore be oper ated in mode 0. in this mode, serial data enters and exits through rxd and a shift clock is output on txd. figure 12 shows how the 8051 is connected to the ad5533b. because the ad5533b shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. the ad5533b re quires its data with the msb first. since the 8051 outputs the lsb first, the transmit routine must take this into account. 8051 * sclk d out sync d in txd ad5533b * * additional pins omitted for clarity rxd p1.1 figure 12. ad5533b to 8051 interface application circuits ad5533b in a typical ate system the ad5533b infinite sample-and-hold is ideally suited for use in automatic test equipment. several ishas are required to control pin drivers, comparators, active loads, and signal timing. traditionally, sample-and-hold devices with droop were used in these applications. these required refreshing to prevent the voltage from drifting. the ad5533b has several advantages: no refreshing is required, t here is no droop, pedestal error is eliminated, and there is no need for extra filtering to remove glitches. overall, a higher level of integration is achieved in a smaller area. see figure 13.
rev. a ad5533b ?5 ishas active load driver comparator formatter compare register stored data and inhibit pattern period generation and delay timing system bus isha parametric measurement unit system bus dut isha isha isha isha isha isha figure 13. ad5533b in an ate system typical application circuit the ad5533b can be used to set up v oltage levels on 32 chann els as shown in the circuit below. an ad780 provides the 3 v refer ence for the ad5533b, and for the ad5541 16-bit dac. a simple 3-wire serial interface is used to write to the ad5541. because the ad5541 has an output resistance of 6.25 k ? (typ), the time taken to charge/ discharge the capacitance at the v in pin is significant. thus an ad820 is used to buffer the dac output. note that it is important to minimize noise on v in and refin when laying out this circuit. ad5533b * offs_in offs_out refin v in sclk din sync av cc dv cc v ss v dd v out 0?1 ad820 cs din sclk * additional pins omitted for clarity ad780 * v out ad5541 * ref av cc figure 14. typical application circuit power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5533b is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5533b is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (v ss , v dd , av cc ) it is recommended to tie those pins together. the ad5533b should have ample supply bypass- ing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. t he power supply lines of the ad5533b should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and s hould never be run near the reference inputs. a ground line routed between the d in and sclk lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). it is essential to minimize noise on v in and refin lines. note it is essential to minimize noise on v in and refin lines. particularly for optimum isha performance, the v in line must be kept noise-free. depending on the noise performance of the board, a noise filtering capacitor may be required on the v in line. if this capacitor is necessary, then for optimum throughput it may be necessary to buffer the source that is driving v in . avoid cross- over of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the cspbga package and to avoid a point load on the surface of this package during the assembly process.
?6 c02715??/02(a) printed in u.s.a. ad5533b rev. a outline dimensions 74-lead chip scale ball grid array [cspbga] (bc-74) dimensions shown in millimeters a b c d e f g h j k l 11 10 9 8 7 6 5 4 3 2 1 1.00 bsc 1.00 bsc bot tom view a1 top view detail a 1.70 max 12.00 bsc sq 10.00 bsc sq a1 corner index area seating plane detail a ball diameter 0.30 min 0.70 0.60 0.50 0.20 max coplanarity compliant to jedec standards mo-192abd-1 revision history location page 9/02?ata sheet changed from rev. 0 to rev. a. term lfbga updated to cspbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . global replaced functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 additions to serial interface table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 replaced figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 additions to power supply decoupling section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 updated bc-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

▲Up To Search▲

Price & Availability of EVAL-AD5533EB

	To Download EVAL-AD5533EB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .